In order to maintain performance in various amplifiers, such as a “Class D” switching amplifiers, the overall delay and dead time in the output stage should be kept low. However, this requires a fast turn on and off of the output field effect transistors (FETs). Turning these devices on and off quickly results in a very fast transition at the output of the amplifier, which can be problematic where electromagnetic interference (EMI) emissions are a concern.
FIG. 1A and FIG. 1B illustrate two conditions of sourcing or sinking a current. A load element is represented by current source 110. In FIG. 1A and FIG. 1B, current entering is controlled by MOS 130, and current coming out is controlled by MOS 120. With low side recycle, the edge will mostly be controlled by the high side device (MOS 120) except for phase shifted loads. A non-phase shifted load is where the current is directly proportional to the voltage across it. This is the case for resistors. Phase shifted load will have inductance of capacitance effect where the current lags or lead the voltage in time.
However, reducing the output transition, i.e. “unsharpening the edges” typically means weakening the gate drive strength; reducing the turn off and on time results in performance degradation. Moreover, there is a distortion issue.
Therefore, it would be useful to reduce the output transition time of amplifier drivers, while maintaining performance.